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data sheet ics844n255akilf revision a november 23, 2011 1 ?2011 integrated device technology, inc. femtoclock? ng crystal-to-lvds clock synthesizer ICS844N255I general description the ICS844N255I is a 6-output clock synthesizer designed for wireless infrastructure clock applications. the device uses idt?s fourth generation femtoclock? ng technology for an optimum of high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. the reference frequency is selectable and the following frequency is supported: 25mhz. the synthesizer generates selectable 156.25mhz, 125mhz, 100mhz, 50mhz and 25mhz clock signals. the device is optimized fo r very low phase noise and cycle to cycle jitter. the synthesized clock frequency and the phase-noise performance are optimized for driving srio 1.3 and 2.0 serdes reference, dsp and host-processor clocks. the device supports a 2.5v voltage supply and is packaged in a small, lead-free (rohs 6) 48-lead vfqfn package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? 4 th generation femtoclock? ng technology ? selectable 156.25mhz, 125m hz, 100mhz, 50mhz and 25mhz output clock signals synthesized from a 25mhz reference frequency ? six differential lvds clock outputs ? crystal interface designed for a 25mhz crystal ? rms phase jitter @ 156.25mhz, using a 25mhz crystal (1mhz - 20mhz): 0.27ps (typical) ? internal regulator for optimum noise rejection ? lvcmos interface levels for the frequency select and output enable inputs ? full 2.5v supply voltage ? lead-free (rohs 6) 48-lead vfqfn package ? -40c to 85c ambient operating temperature block diagram qa nqa qb0 nqb0 qb1 nqb1 qc nqc qd nqd qe nqe pulldown pulldown pulldown pullup pulldown pullup pulldown pulldown pulldown pulldown pulldown osc xtal_in xtal_out ref_clk ref_sel msel fselb fselc fseld fsele noea noeb noec noed noee m 16 20, 25 20, 25 50, 100 50 100 pfd & lpf femtoclock? ng vco 2500mhz pulldown 0 1 5 25mhz 25mhz
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 2 ?2011 integrated device technology, inc. pin assignment gnd ref_clk ref_sel xtal_out xtal_in vdd msel vdd vdd gnd gnd gnd 48 47 46 45 44 43 42 41 40 39 38 37 gnd 1 ICS844N255I 48-lead vfqfn 7.0mm x 7.0mm x 0.925mm, package body k package, top view 36 gnd vddoa 235 vdda qa 334 vdd nqa 433 noee gnda 532 vddoe noea 631 qe noeb 730 nqe vddob 829 gnde qb0 928 fsele nqb0 10 27 vddod qb1 11 26 qd nqb1 12 25 nqd 13 14 15 16 17 18 19 20 21 22 23 24 gndb fselb gndc qc nqc vddoc noec fselc vdd fseld noed gndd
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 3 ?2011 integrated device technology, inc. table 1. pin descriptions note: pulldown and pullup refer to an internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 36, 37, 38, 39, 48 gnd power power supply ground. 2v ddoa power output supply pin for the output qa. 3, 4 qa, nqa output differential clock output a. lvds interface levels. 5gndapower power supply ground for the output qa. 6 noea input pulldown output enable input. see table 3g. lvcmos/lvttl interface levels. 7 noeb input pulldown output enable input. see table 3h. lvcmos/lvttl interface levels. 8v ddob power output supply pin for the bank qb outputs. 9, 10, 11, 12 qb0, nqb0, qb1, nqb1 output differential clock outputs (bank b). lvds interface levels. 13 gndb power power supply ground for the outputs qb0 and qb1. 14 fselb input pulldown frequency select input for bank b outputs. see table 3c. lvcmos/lvttl interface levels. 15 gndc power power supply ground for the output qc. 16, 17 qc, nqc output differential clock output c. lvds interface levels. 18 v ddoc power output supply pin for the output qc. 19 noec input pulldown output enable input. see table 3i. lvcmos/lvttl interface levels. 20 fselc input pullup frequency select input for output qc. see table 3d. lvcmos/lvttl interface levels. 21, 34, 40, 41, 43 v dd power core supply pin. 22 fseld input pulldown frequency select input for output qd. see table 3e. lvcmos/lvttl interface levels. 23 noed input pulldown output enable input. see table 3j. lvcmos/lvttl interface levels. 24 gndd power power supply ground for the output qd. 25, 26 nqd, qd output differential clock output d. lvds interface levels. 27 v ddod power output supply pin for the output qd. 28 fsele input pullup frequency select input for output qe. see table 3f. lvcmos/lvttl interface levels. 29 gnde power power supply ground for the output qe. 30, 31 nqe, qe output differential clock output e. lvds interface levels. 32 v ddoe power output supply pin for the output qe. 33 noee input pulldown output enable input. see table 3k. lvcmos/lvttl interface levels. 35 v dda power analog power supply. 42 msel input pulldown unused control input. connect to logic low level. see table 3a. lvcmos/lvttl interface levels. 44, 45 xtal_in, xtal_out input crystal oscillator interface. xtal_i n is the input, xtal_out is the output. 46 ref_sel input pulldown reference select input. see table 3b for function. lvcmos/lvttl interface levels. 47 ref_clk input pulldown alternative reference clock input. see table 3b. lvcmos/lvttl interface levels.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 4 ?2011 integrated device technology, inc. table 2. pin characteristics function tables symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? table 3a. input reference frequency and pll feedback multiplier reference frequency select reference frequency pll feedback multiplier m msel f ref 0 (default) 25mhz 100 table 3b. pll reference clock select function table input operation ref_sel 0 (default) the crystal interface is selected as reference clock. crystal frequency is 25mhz. 1 the external reference input ref_clk is selected. note: ref_sel is an asynchronous control. table 3c. output qb [1:0] frequency select function table input qb[1:0], nqb[1:0] frequency (mhz) fselb 0 (default) 125 1100 note: fselb is an a synchronous control. table 3d. output qc frequency select function table input qc, nqc frequency (mhz) fselc 0125 1 (default) 100 note: fselc is an asynchronous control. table 3e. output qd frequency select function table input qd, nqd frequency (mhz) fseld 0 (default) 50 125 note: fseld is an asynchronous control.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 5 ?2011 integrated device technology, inc. table 3f. output qe frequency select function table input qe, nqe frequency (mhz) fsele 050 1 (default) 25 note 1: fsele is an asynchronous control. table 3g. noea output enable function table input qa, nqa frequency (mhz) noea 0 (default) output enabled 1 output disabled in high-impedance state note: noea is an asynchronous control. table 3h. noeb output enable function table input operation noeb 0 (default) qb0, nqb0 - qb1, nqb1 outputs are enabled 1 qb0, nqb0 - qb1, nqb1 outputs are disabled (high-impedance) note: noeb is an asynchronous control. table 3i. noec output enable function table input operation noec 0 (default) qc, nqc output is enabled 1 qc, nqc output is disabled (high-impedance) note: noec is an asynchronous control. table 3j. noed output enable function table input operation noed 0 (default) qd, nqd output is enabled 1 qd, nqd output is disabled (high-impedance) note: noed is an asynchronous control. table 3k. noee output enable function table input operation noee 0 (default) qe, nqe output is enabled 1 qe, nqe is disabled (high-impedance) note 1: noee is an asynchronous control.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 6 ?2011 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functio nal operation of product at t hese conditions or any conditions beyond those listed in the dc cha racteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 3.63v inputs, v i crystal inputs other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ja 29c/w (0 mps) storage temperature, t stg -65 c to 150 c esd - human body model, note 1 2000v esd - charged device model, note 1 1500v note 1: according to jedec/jesd 22-a114/22-c101. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddox = 2.5v5%, t a = -40c to 85c note: v ddox denotes v ddoa, v ddob, v ddoc, v ddod, and v ddoe. note: i ddox denotes i ddoa, i ddob, i ddoc, i ddod, and i ddoe. table 4b. lvcmos/lvttl input dc characteristics, v dd = v ddox = 2.5v5%, t a = -40c to 85c note: v ddox denotes v ddoa, v ddob, v ddoc, v ddod, and v ddoe. item rating symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5v 2.625 v v dda analog supply voltage v dd ? 0.24 2.5v v dd v v ddox output supply voltage 2.375 2.5v 2.625 v i dd power supply current 140 ma i dda analog supply current 24 ma i ddox output supply current 111 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current noe[a:e], ref_clk, ref_sel, fselb, fseld, msel v dd = v in = 2.625v 150 a fselc, fsele v dd = v in = 2.625v 5 a i il input low current noe[a:e], ref_clk, ref_sel, fselb, fseld, msel v dd = 2.625v, v in = 0v -5 a fselc, fsele v dd = 2.625v, v in = 0v -150 a
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 7 ?2011 integrated device technology, inc. table 4c. lvds dc characteristics, v dd = v ddox = 2.5v5%, t a = -40c to 85c note: v ddox denotes v ddoa, v ddob, v ddoc, v ddod, and v ddoe. table 5. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf drive level 205 w
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 8 ?2011 integrated device technology, inc. ac electrical characteristics table 6. ac characteristics, v dd = v ddox = 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized with 25mhz crystal, unless otherwise noted. note: v ddox denotes v ddoa, v ddob, v ddoc, v ddod, and v ddoe. note 1: please refer to the phase noise plots. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew within a bank of outputs at the same voltage and with equal load conditions. symbol parameter test conditio ns minimum typical maximum units f out output frequency qa 125 156.25 mhz qb, qc 100 125 mhz qd 25 50 mhz qe 25 50 mhz f ref reference frequency 25 mhz t jit(?) rms phase jitter (random); note 1 156.25mhz integration range: 1mhz ? 20mhz 0.27 0.34 ps integration range: 12k hz ? 20mhz 0.30 0.39 ps 125mhz integration range: 12k hz ? 20mhz 0.30 0.43 ps integration range: 10khz ? 1.5mhz 0.26 0.40 ps integration range: 1.5mhz ? 62.5mhz 0.25 0.40 ps 100mhz integration range: 12k hz ? 20mhz 0.31 0.43 ps integration range: 10khz ? 1.5mhz 0.26 0.38 ps integration range: 1.5m hz ? 50mhz 0.28 0.42 ps n single-side band noise power 156.25mhz offset: 100hz -58 dbc/hz offset: 1khz -117 dbc/hz offset: 10khz -127 dbc/hz offset: 100khz -133 dbc/hz offset: 20mhz -157 dbc/hz t jit(cc) cycle-to-cycle jitter; note 2 100mhz 6.8 ps 125mhz 6.7 ps 156.25mhz 7.3 ps tsk(b) bank skew; note 2, 3 qb[0:1], nqb[0:1] 816ps t r / t f output rise/fall time 20% to 80% 250 650 ps t lock pll lock time 10 ms odc output duty cycle 48 52 %
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 9 ?2011 integrated device technology, inc. typical phase noise at 156.25mhz noise power dbc hz offset frequency (hz)
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 10 ?2011 integrated device technology, inc. parameter measureme nt information lvds output load ac test circuit cycle-to-cycle jitter output duty cycle/pulse width/period rms phase jitter bank skew output rise/fall time scope qx nqx 3.3v5% power supply +? float gnd lvds v dda v dd, v ddox nqx qx ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles t pw t period t pw t period odc = x 100% nqx qx offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power t sk(b) nqb0 qb0 nqb1 qb1 20% 80% 80% 20% t r t f v od nqx qx
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 11 ?2011 integrated device technology, inc. parameter measurement in formation, continued lock time differential output voltage setup offset voltage setup ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? ? ? v os / ? v os v ddo
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 12 ?2011 integrated device technology, inc. applications information interface to idt srio switches the ICS844N255I is designed for driving the differential reference clock input (ref_clk) of idt?s srio 1.3 and 2.0 switch devices. the lvds outputs of the ICS844N255I have the low-jitter, differential voltage and impedance characteristics required to provide a high-quality 156.25mhz clock signal for both srio 1.3 and 2.0 switch devices. please refer to figure 1 for a suggested interfaces. in figure 1, the ac-coupling capacitors are mandatory by the idt srio switch devices. the differential ref_clk input is internally re-biased and ac-terminated. the interface circuit is optimized for 50 ? transmission lines and generates the voltage swing required to reliably drive the clock reference input of a idt srio switch. please refer to idt?s srio device datasheet for more details. figure 1 shows the recommended interface circuit for driving the 156 .25mhz reference clock of an idt srio 2.0 switch by a lvds output of the ICS844N255I. the lv ds-to-differential interface as shown in figure 1 does not require any external termination resistors: the ICS844N255I driver contains an internal source termination at qa0 and qa1. the differential ref_ clk input contains an internal ac-termination (r l ) and re-bias (v bias ). + - ref_clk ICS844N255I idt srio 1.3, 2.0 switch l i l i c i c i v bias r l r l qan nqan t= 50 lv d s ref_clk_p ref_clk_n figure 1. lvds-to-srio 2.0 reference clock interface recommendations for unused input and output pins i nputs: lvcmos control pins all control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. ref_clk input for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 13 ?2011 integrated device technology, inc. overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 14 ?2011 integrated device technology, inc. lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o z t z o z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination lvds termination
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 15 ?2011 integrated device technology, inc. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 16 ?2011 integrated device technology, inc. schematic layout figure 5 shows an example of ICS844N255I application schematic. in this example, the device is operated at v dd = v ddoa = v ddob = v ddoc = v ddod = v ddoe = 2.5v. the 16pf parallel resonant 25mhz crystal is used. the load capacitance c1 = 15pf and c2 = 15pf are recommended for frequency accuracy. depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. for this device, the crystal load capacitors are r equired for proper operation. as with any high speed analog circuitry, the power supply pins are vuln erable to noise. to achieve optimum jitter performance, power supply isolation is required. t he ICS844N255I provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the pla cement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pi n filter should be placed on the device side of the pcb and the ot her components can be placed on the opposite side. vdda vddo vddo vd d qe noe e qd fse le nqe ref _sel nqd ms el c1 9 0. 1 uf (u1:32) vddo c20 0. 1 uf (u1:34) c21 10uf (u1:40) c22 0.1uf (u1:43) (u1:41) vdd (u1:8) (u1:2) (u1:21) c14 10uf 2. 5 v 2. 5 v c13 0. 1 uf murata, b lm18bb221s n1 fb2 1 2 c12 0.1uf c10 0. 1 uf murata, b lm18bb221s n1 fb3 1 2 c11 10uf c17 0. 1 uf c18 0.1uf (u1:27) (u1:18) c15 0.1uf c16 0.1uf ru1 1k ru2 not install rd2 1k vdd vdd rd1 not install to lo gic inpu t pins logic input pin examples set logic input to '0' to log ic inpu t pins set logic input to '1' r4 33 q1 lvcmos_driver ref_clk zo = 50 vddo vd d nqa qa qa vddod=v d doe=2. 5v zo_diff = 100 ohm z o _d i f f = 10 0 o h m vddoa =vddob=v ddoc =2.5v nq e + - qe + - alternate lvds termination r6 50 lv d s te rm i n at io n r7 50 nqa r5 10 0 vdd=2. 5v c5 0.1uf x1 25mhz 1 6 p f c2 15pf c1 15pf xtal_in xtal_out vd d u1 gnd 37 gn d 38 gnd 39 vd d 40 vdd 41 mse l 42 vdd 43 xta l_ i n 44 xtal_out 45 ref_sel 46 re f _ cl k 47 gnd 48 gnd 1 vddoa 2 nq a 4 qa 3 gnda 5 no e a 6 no e b 7 vddob 8 qb0 9 nq b 0 10 qb1 11 nq b 1 12 gndd 24 no e d 23 fs eld 22 vd d 21 f sel c 20 noe c 19 vddoc 18 nqc 17 qc 16 gndc 15 fsel b 14 gndb 13 gnd 36 vdda 35 vd d 34 no e e 33 vddoe 32 qe 31 nqe 30 gnde 29 fs ele 28 vddod 27 qd 26 nqd 25 epad 49 vddo noeb noea qb1 nqb0 qb0 nqb1 fsel b nqc qc noec f sel c fs eld vddoc noe d c4 10uf c3 0.1uf vd d r1 5 - 10 figure 5. ICS844N255I application schematic power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed fo r wide range of noise frequencies. this low-pass filter starts to atte nuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not config uration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 17 ?2011 integrated device technology, inc. power considerations this section provides information on power dissipati on and junction temperature for the ICS844N255I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS844N255I is the sum of the core power plus the analog power plus the power dissipation i n the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. power (core) max = v dd_max * (i dd_max + i dda_max ) = 2.625v * (140ma + 24ma) = 430.5mw power (outputs) max = v ddo_max * i ddo_max = 2.625v * 111ma = 291.375mw total power_ max = 430.5mw + 291.375mw = 721.875mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow of and a multi-layer board, the appropriate value is 29c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.722w * 29c/w = 105.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 48 lead vfqfn, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 29.0c/w 25.4c/w 22.8c/w
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 18 ?2011 integrated device technology, inc. reliability information table 8. ja vs. air flow table for a 48-lead vfqfn transistor count the transistor count for ICS844N255I is: 21,109 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 29.0c/w 25.4c/w 22.8c/w
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 19 ?2011 integrated device technology, inc. package outline and package dimensions package outputline -k suffix for 48 lead vfqfn table 9. packagedimensions for 48 lead vfqfn reference document: id t drawing #psc-4203 n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1) all dimensions in millimeters symbol minimum nominal maximum n 48 a 0.8 0.9 a1 0 0.02 0.05 a3 0.2 ref. b 0.18 0.25 0.30 d & e 7.00 basic d1 & e1 5.50 basic d2 & e2 5.50 5.65 5.80 e 0.50 basic r 0.20~0.25 zd & ze 0.75 basic l 0.35 0.40 0.45
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer ics844n255akilf revision a november 23, 2011 20 ?2011 integrated device technology, inc. ordering information table 10. ordering information table note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configur ation and are rohs compliant. part/order number marking package shipping packaging temperature 844n255akilf ics844n255ail lead-free, 48-lead vfqfn tray -40 c to 85 c 844n255akilft ics844n255ail lead-free, 48-lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or spec ifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS844N255I data sheet femtoclock ? ng crystal-to-lvds clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt?s products for any particular purpose, an im plied warranty of merchantabilit y, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt l ogo are registered trademarks of idt. ot her trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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